Fig. 1. Schematic of the chip, and the definition of D.

Fig. 2. Process flow for the realization of SBWs. (a) The mask deposition, photolithography process, and chemical etching and backside mask deposition. (b) The thermal Ag+/Na+ exchange. (c) The chemical etching of both masks. (d) The backside dielectric mask deposition. (e) The electric-assisted ion-diffusion.

Fig. 3. (a) Buried depth. (b) The output cross-section view of the waveguides.

Fig. 4. The schematic of the different regions of the SBW.

Fig. 5. The measured IL of the SBWs, with the different lengths of the backside mask.