The photocurrent and dynamic output impedance of MW detectors differentiate from LW by several orders of magnitude. For the requirement in integrating time and readout SNR, a designing scheme of a highly integrated readout circuit for 320×256 dual-color infrared focal plane arrays(IRFPAs) was proposed by adopting a sharing methods between pixel capacitors. In this circuit, the DI structure was chosen as the MW injection stage and the BDI structure was used for LW. The buffered amplifier had a unilateral structure which always performanced with high gain, low consumption and low noise, thus it reduced the input impedance and improved the injection efficiency. The chip was designed and manufactured based on HHNEC 0.35 μm 2P4M standard CMOS process. In the testing process, this chip presented a normal operating state and was sensitive enough to the change of illumination. The total effective charge capacity reached 70 Me-/pixel. Under 2.5 MHz output speed, the output swings of MW and LW were larger than 2 V and the nonlinearity less than 1%. The total power consumption was less than 170 mW when working with the frame rate of 100 f/s.