For a variety of simulation needs of the CCD camera combination in a remote sensing satellite and for three different simulation tasks in ground electronic measurement systems and telemetry data link on board, a type of camera simulation source for different types of CCD cameras is developed with programmable logic devices, high speed array storage technology, Phase Locked Loop(PLL) frequency adjustment technology and the software and hardware programmable image processing technology. The system supports cascading multiple devices, 4-channel parallel 16 bit LVDS, 4 serial LVDS and 4 serial NECL signals, in which the pixel frequency of parallel LVDS data in per channel can be ranged from 0.3 MHz to 200 MHz in a step of 0.1 MHz and the capacity of single cycle output is up to 8 TB. In addition, through a simple configuration, the system can produce the play back data of the remote sensing camera according to the CCSDS protocol and can adjust the output signal frequency and data clock phase in real time. The system has been successfully applied in many types of space camera development tests, and it enhances the efficiency of space CCD camera development, equipment utilization and testing certification means.