Hao YANG, Shuxiang LU, Huaishen LI, Shaojia CHEN, Bin TANG, Xiuku WANG, Lixin ZENG, Li YU, Zhiyong WAN, Huiyin LIU, Zhijia SUN. Performance test of front-end ASIC chip CSNS_VASD developed for China Spallation Neutron Source[J]. NUCLEAR TECHNIQUES, 2024, 47(7): 070401
- NUCLEAR TECHNIQUES
- Vol. 47, Issue 7, 070401 (2024)
Fig. 1. Schematic diagram of the second-generation neutron scintillator detector's structure for CSNS
Fig. 2. Waveform of neutron signal
Fig. 3. Waveform of γ signal
Fig. 4. Schematic diagram of the signal processing method
Fig. 5. Schematic diagram of the test system
Fig. 6. Photograph of ASIC test board
Fig. 7. Digital readout board
Fig. 8. Configuration sequence diagram of CSNS_VASD chip
Fig. 9. Flow chart of data processing
Fig. 10. Distribution diagram of the nonlinear error
Fig. 11. Distribution diagram of the gain
Fig. 12. Snapshot of detection efficiency test of the detector in neutron beamline of CSNS
Fig. 13. Detector's uniformity before optimization
Fig. 14. Detector's uniformity after optimization
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Table 1. Noise test
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