In realtime networkstraffic characteristic with burstiness constraints is one of the key QoS (Quality of Service) factors in the worst case.Using timed automata to model the traffic can reflect the uncertainty under the constraints by arrival curves.We adopted hardware description language to describe timed automata formal modelsand studied correspondence between hardware logic and timed automata model.The method took the advantages of programmable array chipsfully represented the concurrent behaviors between timed automataand then implemented the hardwareintheloop testing and detection.With such a methodwe simulated the virtual link traffic generation in realtime network.Some typical test results indicated that the model can constrain the traffic characteristics of virtual linkwhich proves the feasibility of the hardware implementation method.