With the exponentially growing data traffic, the quest for energy-efficient and scalable on-chip optical communication systems has become more imperative [1,2]. Silicon photonics plays a pivotal role in optical interconnects and optical computing by offering high bandwidth and large-scale integration on a matured platform that is compatible with CMOS industry [3]. On-chip wavelength division multiplexing (WDM) allows simultaneous modulation and detection at multiple wavelengths through a single physical channel, which can significantly improve the bandwidth density of silicon photonics [4,5]. As the ideal device for on-chip WDM, the silicon microring modulator (Si-MRM) offers an ultra-compact footprint, low energy consumption, and wavelength multiplexing/demultiplexing simply by changing the radius of the ring [6]. By coupling multiple Si-MRMs with slightly different radii to a single bus waveguide [7], it will enable electro-optic (E-O) modulation at various wavelengths concurrently, thereby maximizing the bandwidth density of photonic integrated circuits (PICs). Several on-chip WDM systems using a Si-MRM array based on reversed PN junctions have demonstrated large-scale integration with an aggregated bandwidth by leveraging the top-quality fabrication capability offered by silicon photonics foundries [8–17]. However, the E-O efficiency of Si-MRMs by commercial foundries is limited by the relatively weak plasma dispersion of silicon and the low capacitance density of reversed PN junctions as discussed in Ref. [18]. To address such intrinsic weakness, silicon photonic devices driven by the metal-oxide-semiconductor capacitor (MOSCAP) incorporating a thin insulator layer, such as hafnium oxide (${\mathrm{HfO}}_2$), provide improved E-O efficiency [19,20]. Moreover, MOSCAP devices allow heterogeneous integration with other semiconductors such as III-V compounds, transparent conductive oxides (TCOs), and graphene, which offers larger refractive index modulation [21–23]. Previous works on MRMs utilizing MOSCAP gated by various materials have demonstrated enhanced E-O modulation performance [24–28]. However, these reports only covered individual Si-MRM devices, which do not answer uncertainties of scalability to large-scale integration considering the challenge of process compatibility of heterogenous integration.

In this paper, we demonstrate a $1\times 4$ MOSCAP-driven Si-MRM array heterogeneously integrated with high-mobility titanium-doped indium oxide (ITiO), which can perform on-chip WDM modulation. The ITiO-gated MOSCAP Si-MRM performs non-return-to-zero (NRZ) modulation with open eye diagrams up to 30 Gb/s. Additionally, it showcases an enhanced E-O efficiency $V_{\pi }·L$ of $0.12\mathrm{V}·\mathrm{cm}$, surpassing traditional Si-MRMs using PN junctions where $V_{\pi }·L$ often exceeds $0.5\mathrm{V}·\mathrm{cm}$ [12,29]. Our previous work has shown that a MOSCAP-driven Si-MRM with a gate bias can obtain high E-O efficiency, enabling substantial wavelength tuning, which can effectively compensate temperature variations and fabrication errors [30,31]. In this work, we introduce a moderate gate bias to fine-tune the resonant spectra of Si-MRMs with minimal power consumption. This approach demonstrates the feasibility of tailored modulation performance while maintaining equally spaced working wavelengths for possible integration with comb lasers. Ultimately, the $1\times 4$ Si-MRM array achieves a throughput of $(3\times 25+1\times 15)\mathrm{Gb}/\mathrm{s}$ with a maximum E-O bandwidth of 14 GHz. The MOSCAP Si-MRM array was fabricated using Intel’s high-volume manufacturing (HVM) process, and the TCO layer was patterned with the university fabrication facility. This work demonstrates a heterogeneous integration of the MOSCAP Si-MRM array for on-chip WDM, marking a significant milestone of the development of MOSCAP modulators towards large-scale PICs.

The ITiO-gated Si-MRM array is illustrated in Fig. 1(a) with four ring resonators, of which the radii vary among 6.00 μm, 6.02 μm, 6.04 μm, and 6.06 μm to operate at four equally spaced wavelengths. As discussed in our previous work [31], 10 nm ${\mathrm{HfO}}_2$, which is a high-$\kappa$ dielectric, is chosen for its ability to provide a high capacitance density, thereby enhancing the E-O efficiency of MOSCAP MRMs while ensuring a low leakage current. For the gate material, a high-mobility TCO such as ITiO plays a critical role in improving the conductivity of the gate layer and reducing optical loss to the silicon waveguide. Therefore, the high-mobility ITiO is essential to enhance the RC-delay limited bandwidth and the quality factor (Q-factor) of the MRM. In this work, the active region of the Si-MRM comprises an $\mathrm{ITiO}/{\mathrm{HfO}}_2/\mathrm{Si}\mathrm{MOSCAP}$, with ITiO serving as the gate and ${\mathrm{HfO}}_2$ as the insulator, as shown in the cross-sectional view of the active region of the Si-MRM in Fig. 1(b). The silicon ring waveguide acts as the bottom substrate of the MOSCAP, featuring a 300 nm thick silicon rib waveguide with a 100 nm slab thickness. The waveguide width of the microring is designed to be 300 nm to optimize E-O efficiency [31].

In contrast to our prior work [31], the doping profile of silicon in this work is properly designed to enhance the modulation speed. With higher doping to the silicon waveguide, it lowers the series resistance and increases the loss of the microring, which subsequently reduces both the RC time constant and the photon lifetime. Consequently, this approach enhances both RC-limited and photon-lifetime-limited bandwidths. However, the reduced Q-factor also requires a higher driving voltage to operate and lowers the energy efficiency. In our work, the doping profile is designed to maintain a Q-factor above 10,000 before depositing ITiO to the silicon microring. The entire Si-MRM incorporates a background Si p-doping ($1\times {10}^{17}{\mathrm{cm}}^{-3}$). The top of the ring waveguide, including part of the silicon slab, features Si $\mathrm{p}+$ doping ($3\times {10}^{18}{\mathrm{cm}}^{-3}$). Additionally, the metal contact region is doped with Si $\mathrm{p}++$ ($1\times {10}^{20}{\mathrm{cm}}^{-3}$) and is approximately 600 nm away from the ring waveguide.

Figure 3 showcases the co-fabricated $1\times 4$ ITiO-gated MOSCAP Si-MRM array. In Fig. 3(a), there are four cascaded passive silicon microring resonators coupled to a bus waveguide with two grating couplers. Figure 3(b) displays the completed Si-MRM array after undergoing the comprehensive TCO patterning process. Additionally, the inset image of Fig. 3(b) offers detailed perspectives of the active region, illustrating the ITiO coverage to the silicon microring waveguide to form the $\mathrm{ITiO}/{\mathrm{HfO}}_2/\mathrm{Si}\mathrm{MOSCAP}$ structure. Figure 3(c) presents the measured transmission spectra for on-chip WDM modulation. Due to slight variations in the radius of each silicon microring, four resonant wavelengths are fitted within a free spectral range (FSR) of 11.6 nm. Additionally, the inset image of Fig. 3(c), which was captured by an infrared camera, highlights the light confinement observed in one of the Si-MRMs at its respective resonant wavelength.

Each ITiO-gated MOSCAP Si-MRM in the array was individually characterized. In Fig. 4(a), the normalized transmission spectra of these Si-MRMs are presented under various gate biases. The increment in bias voltages induces a reduction in the effective index of the waveguide, consequently causing a blue shift of the microring resonance. The MOSCAP Si-MRM array showcases E-O efficiency ranging from 80 pm/V to 105 pm/V, with an average $V_{\pi }·L$ of $0.12\mathrm{V}·\mathrm{cm}$. However, it exhibits relatively low Q-factors from 2100 to 2600 with an estimated optical loss of 340 dB/cm, which is primarily attributed to the silicon waveguide roughness and free carrier absorption by ITiO deposited on top of it. Since the radii are approximately 6 μm, these microrings are more sensitive to sidewall roughness [32]. The ${\mathrm{SiO}}_2$ cladding etch during fabrication [as shown in Fig. 2(b)] may have introduced additional roughness to the silicon microring waveguide. Therefore, the Q-factors of these microrings are lower than our previous work, where a larger radius of 8 μm was utilized [27].

Furthermore, Fig. 4(b) illustrates the E-O transfer curve at different working wavelengths for each channel, represented by different colors. The observed non-linearity of the E-O transfer curve is attributed to the Lorentz shape of the microring transmission. The E-O efficiency and Q-factor play crucial roles in determining the extinction ratio (ER) of the modulation. The E-O efficiency influences the shift in the transmission spectrum, while the Q-factor affects the sharpness of the transmission spectrum. For example, with an insertion loss (IL) of 3 dB, both channel 1 (CH1) and channel 2 (CH2) attain an ER above 6 dB with a $2V_{\mathrm{pp}}$ voltage swing. In contrast, CH3 and CH4, which have relatively lower Q-factors and E-O efficiencies, achieve an ER of less than 6 dB under the same IL and voltage swing. To ensure efficient E-O modulation across every channel within the modulator array, a $V_{\mathrm{pp}}$ of 3 V is chosen for all channels. This choice is intended to achieve optimal and practical modulation performance, adhering to the criteria of an IL below 3 dB and an ER above 6 dB [33].

The optical input was generated from a tunable laser and coupled into and out of the modulator array using vertical grating couplers. The RF signals were transmitted to the devices through a $50\text{-}\mathrm{\Omega }$ terminated probe. The E-O frequency response ($S_{21}$) of the fabricated ITiO-gated MOSCAP Si-MRM was measured using a vector network analyzer (VNA), revealing a 3 dB bandwidth of 14 GHz, as shown in Fig. 5(a). For the characterization of data transmission, each ITiO-gated MOSCAP Si-MRM was driven by NRZ pseudorandom binary sequence (PRBS) signals generated by an arbitrary waveform generator (AWG) sequentially. The signal traversed a path including an RF amplifier (the AWG output is limit to 2 V), a bias tee, and a $50\text{-}\mathrm{\Omega }$ terminated probe before reaching the respective device. Subsequently, the modulated optical signals were amplified by an optical fiber amplifier before being detected by a digital communication analyzer (DCA). As an illustrative example, in the characterization of CH2, the tunable laser set the optical input wavelength to 1316.29 nm, while CH2 was driven by $3V_{\mathrm{pp}}$ ($0–3\mathrm{V}$) NRZ PRBS signals. Figure 5(b) shows the resulting optical eye diagrams of CH2 at various data rates. At lower data rates, such as 1 Gb/s and 5 Gb/s, NRZ with rectangular transitions from the AWG was used to drive the modulator as it provides good signal integrity. At higher data rates ($>10\mathrm{Gb}/\mathrm{s}$), NRZ with raised cosine transitions was employed to reduce inter-symbol interference (ISI), minimizing signal distortion. It shows the eye diagram remaining open to a data rate of 30 Gb/s.

To prove the working condition with equal wavelength spacing that may be compatible with comb lasers [34], we intentionally set the optical input wavelengths at 1313.34 nm, 1316.29 nm, 1319.24 nm, and 1322.19 nm, respectively. This allowed us to thoroughly characterize each channel within the modulator array for on-chip WDM application. Figure 6(a) shows the measured leakage current of the ITiO-gated MOSCAP Si-MRM. Within 8 V, such a device exhibited a low leakage current of less than 100 pA. However, beyond 8 V, the leakage dramatically increased, approaching breakdown, which is detrimental to device operation. Upon characterizing each channel with a $3V_{\mathrm{pp}}$ voltage swing (ranging from 0 V to 3 V) at varying wavelengths, CH2 exhibited the anticipated modulation performance at 1316.29 nm with an IL less than 3 dB and an ER exceeding 6 dB, as shown in Fig. 6(b). Conversely, under identical driving conditions, CH3 and CH4 exhibited unexpected IL values greater than 3 dB, as illustrated in Fig. 6(c). To address this issue, additional gate biases were introduced to shift the spectra, resulting in an approximate 40 pm shift for CH3 and 80 pm shifts for CH4. The maximum wavelength shift of each channel induced by the ITiO MOSCAP is around 800 pm, which is limited by its breakdown voltage. Although not as large as thermal tuning, gate voltage tuning is much more energy efficient. Subsequently, applying the gate bias effectively reduced the IL to below 3 dB while maintaining an ER greater than 6 dB. However, CH1 displayed significant resonant spectrum offset, leading to modulation on the opposite side of the resonant spectra compared to other channels at the CH1 working wavelength (1313.34 nm), as shown in Fig. 6(b). While tuning with a high gate bias (around 5–6 V) might address this issue, it would bring the device close to the breakdown voltage post-tuning. Therefore, CH1 was characterized without any gate bias tuning. Despite lacking gate bias tuning and exhibiting modulation on the opposite side of the resonant spectra compared to other channels, CH1 achieved an IL of less than 3 dB and an ER exceeding 6 dB at 1313.34 nm. Figure 6(d) illustrates the modulation of the four channels with a $3V_{\mathrm{pp}}$ driving voltage at different working wavelengths after gate bias tuning. Three channels demonstrated clear open-eye diagrams up to a data rate of 25 Gb/s. Despite the same expectations on modulation performance, CH4’s open-eye diagram extended only to 15 Gb/s. CH4 showed a lower data rate likely due to fabrication imperfections specific to that channel. Since the chip was fabricated by combining Intel’s HVM and our own nanofabrication process, it is challenging in terms of reliability. Therefore, optimizing the fabrication process to ensure more consistent performance across all channels will be the focus of our future work. Through an optimized fabrication process, each ITiO-gated MOSCAP Si-MRM holds the potential to enhance the Q-factor and reduce the driving voltage to sub-volt levels as individual MRM [27].

The leakage current primarily determines the static power consumption associated with gate bias tuning. At low gate biases, the leakage current for the ITiO-gated MOSCAP Si-MRM is approximately 25 pA, as illustrated in Fig. 6(a). Utilizing this leakage current alongside the E-O efficiency, we estimate a gate bias tuning power consumption of approximately 312 pW/nm. This estimation shows that achieving a total resonant wavelength shift of 120 pm in this MOSCAP Si-MRM array would require approximately 37 pW. In contrast, employing conventional thermal tuning to adjust the resonant spectra, typically operating with the power consumption of 3.1 mW/nm [35], would cost approximately 0.37 mW for the same resonant wavelength shift. Therefore, gate bias tuning offers an exceptionally efficient approach for sustaining the desired working wavelength and achieving anticipated modulation performance in on-chip WDM systems.

In conclusion, this work demonstrated a $1\times 4$ ITiO-gated MOSCAP Si-MRM array. Our experimental results highlighted remarkable E-O efficiency $V_{\pi }·L$ of $0.12\mathrm{V}·\mathrm{cm}$, showcasing the feasibility of achieving tailored modulation performance while preserving equally spaced working wavelengths. By employing the gate bias technique to fine-tune the resonant spectra of Si-MRMs, we have achieved data rates of $(3\times 25+1\times 15)\mathrm{Gb}/\mathrm{s}$, with potential capability of reaching $4\times 25\mathrm{Gb}/\mathrm{s}$ at a sub-volt $0.8V_{\mathrm{pp}}$. The adoption of gate bias tuning offers significant advantages in power efficiency over traditional thermal tuning methods, particularly crucial in the realm of large-scale on-chip WDM optical interconnects.

Furthermore, this work demonstrated a co-fabrication approach by combining Intel’s HVM silicon photonics process with a university fabrication facility for TCO patterning, creating heterogeneously integrated silicon PIC driven by high-mobility ITiO, which will enable high bandwidth density Si-PICs with better energy efficiency for future optical communication and computation systems. Although there is still significant room for optimization of the co-fabrication approach, successful demonstration of the $1\times 4$ ITiO-gated Si-MRM array with the capability of on-chip WDM modulation accomplished a milestone to MOSCAP-driven Si-PICs.

Acknowledgment. The authors would like to acknowledge the Baylor University Mearse Endowment for equipment support for high-speed optoelectronics characterization, and the Center for Microscopy and Imaging (CMI) at Baylor University for device imaging. Besides, the authors acknowledge Intel’s photonics fab, Materials Synthesis and Characterization Facility (MaSC), and the Electron Microscopy Facility at Oregon State University for device fabrication. MaSC is part of the Northwest Nanotechnology Infrastructure, a National Nanotechnology Coordinated Infrastructure site at Oregon State University supported in part by the National Science Foundation (grant NNCI-1542101). The authors acknowledge Duanni Huang and James Jaussi for technical discussions. Furthermore, the authors would like to thank Nabila Nujhat for assistance with device fabrication and Benjamin Kupp and John F. Conley, Jr., for the HfO2 deposition using ALD.