【AIGC One Sentence Reading】:We propose an EO comb cloning-based fronthaul solution for 6G RAN, achieving Tb/s data transmission and ps-level clock synchronization.
【AIGC Short Abstract】:This work proposes an electro-optic comb cloning technique for fronthaul systems, achieving picosecond-level timing jitter clock distribution and Tb/s data transmission. It simplifies DSP by enabling clock synchronization and a self-homodyne structure, supporting WDM transmission and laying the foundation for a 6G fronthaul architecture.
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Abstract
Beyond providing user access to the core network, the radio access network (RAN) is expected to support precise positioning and sensing for emerging applications such as virtual reality (VR) and drone fleets. To achieve this, fronthaul—the link connecting the central units/distributed units (CUs/DUs) to wireless remote units (RUs) in centralized RAN—must realize both high-capacity transmission and low-timing-jitter clock synchronization between RUs. However, existing solutions fall short of supporting these functions within one simple, cost-effective network. In this work, we propose a solution that simultaneously achieves picosecond-level timing jitter clock distribution and Tb/s data transmission with simplified DSP, using an electro-optic (EO) comb cloning technique to enable multifunctionality in fronthaul systems. Through the delivery of pilot comb lines, a 1 ps (integrated from 1 Hz to 40 MHz) low-timing-jitter 100 MHz clock is distributed by the beating of adjacent pilot comb lines and subsequent frequency dividing, realizing frequency synchronization between the CUs/DUs and RUs. Moreover, the delivery of pilot comb lines also facilitates self-homodyne structures through EO comb cloning, and supports wavelength division multiplexing (WDM) transmission with a line capacity of 2.88 Tb/s and a net capacity of 2.5 Tb/s. Thanks to the clock-synchronized and self-homodyne structure, DSP is streamlined, with digital timing recovery, carrier phase estimation, and frequency offset estimation all omitted. This work lays the technical foundation for implementing a 6G WDM fronthaul architecture that integrates ultra-wide wireless bandwidth with precise positioning and sensing.
1. INTRODUCTION
As wireless communication services evolve into the 6G era, mobile user data capacity was projected to reach 77 exabytes per month in 2022, continuing to grow exponentially [1]. In this context, the radio access network (RAN) plays a critical role in ensuring seamless and stable access to the core network for a vast number of user devices. Within the RAN architecture, the fronthaul—the link connecting the central units/distributed units (CUs/DUs) to the remote units (RUs)—is particularly crucial. It directly transmits the aggregated wireless signals from the CUs/DUs to the RUs, where the data is processed and subsequently transmitted via antennas. As such, the fronthaul is key to enabling the efficient delivery of RAN’s services [2].
Along with the capacity surge, at the same time, RAN is expected to evolve beyond its basic communication function and enable advanced functions such as clock synchronization between RUs. This can support applications like multi-node collaborative sensing and ground-based sub-meter precise positioning, which are critical for technologies such as virtual reality (VR) headsets, autonomous vehicle fleets, and drone swarms [3,4]. The key enabler for these is the 5G New Radio positioning protocol, which standardizes time difference of arrival (TDOA) as the cellular positioning method [5]. TDOA works by translating time-of-arrival measurements into distances, which are then used to determine a user’s position through multilateration. The accuracy of this positioning method depends heavily on precise clock synchronization among the antennas connected to different RUs within the RAN. Specifically, the positioning accuracy is directly related to the synchronization precision, as indicated by the equation , where is the positional error and is the clock synchronization error. Achieving sub-meter positioning requires synchronization at the sub-nanosecond level. In this context, RAN has emerged as a promising alternative or backup solution to traditional terrestrial positioning systems. Before, the Global Navigation Satellite System (GNSS) has been the primary method for time synchronization and positioning with its ideal accuracy approaching centimeter level [6], yet its practical accuracy is often limited by meter-level errors caused by multipath propagation [7] and obstructed sky views [8]. These limitations are further compounded in indoor scenarios, which is highlighted in the 3GPP standard [9]. Additionally, GNSS systems are vulnerable to cyber threats such as jamming and spoofing [10], which undermines their reliability for applications requiring stable and secure positioning services. In contrast, RAN’s widespread deployment and ability to provide secure connectivity, even in challenging urban indoor scenarios, position it as a strong alternative to GNSS.
Nevertheless, current RAN solutions are unable to address both capacity and clock distribution demands within a single architecture. Commercial solutions, such as synchronous Ethernet (Sync-E) combined with the Precision Time Protocol (PTP), are commonly employed. Specifically, the clock of the RUs is synchronized with the bit clock of the received common public radio interface (CPRI) signal, while PTP is used for time-stamping and compensating for the transit time between the clock source and slave clock to obtain accurate timing information [11]. However, due to frequency wander caused by the jitter attenuator in the phase-locked loop, the achievable synchronization accuracy is limited to (parts per billion) [12,13]. Meanwhile, the White Rabbit technology offers an improvement by extending PTP in a backward-compatible manner to achieve sub-nanosecond synchronization accuracy [14]. However, it is constrained by its reliance on optical 1.25 Gb/s Ethernet equipment [15], which does not meet the data rate requirements of standard data streaming networks and requires additional dedicated networks. Another potential solution, phase caching, achieves sub-picosecond synchronization with a data rate of 25.6 Gb/s using on-off keying (OOK) signals [16]. Despite these advancements, these data streams are insufficient to address the growing capacity demands, as they cannot be integrated into the required coherent architectures and advanced radio-over-fiber signal formats. There is a clear need for a scalable, simple, and cost-effective RAN structure that can simultaneously support coherent architecture-enabled high-capacity transmission and high-precision clock distribution within a unified network.
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In this paper, we present an integrated fronthaul architecture that incorporates Tb/s, simplified-DSP transmission with picosecond-level timing jitter frequency synchronization between RUs using EO comb cloning, as illustrated in Fig. 1. Our approach leverages an EO comb to generate multiple wavelength division multiplexing (WDM) channels. By replicating the comb through the transmission of pilot comb lines, we establish an identical EO comb as a local oscillator, enabling a self-homodyne structure that eliminates the need for carrier phase and frequency offset estimation in the DSP [18]. Furthermore, CUs/DUs’ clock information can be loaded onto pilot comb lines and delivered to RUs. And through the beating of adjacent pilot comb lines and subsequent frequency dividing at RUs, only a 1 ps low-timing-jitter (integrated from 1 Hz to 40 MHz) 100 MHz clock can be retrieved. This synchronization facilitates optical clock alignment between transmitters (Tx) and receivers (Rx), thereby obviating the need for digital timing recovery in the DSP. Combined with omitted carrier phase estimation and frequency offset estimation, which is enabled by the self-homodyne structure, DSP is greatly simplified by 36%. This results in a significant reduction in power consumption, as DSP typically accounts for a substantial portion of total power usage [19]. Furthermore, the synchronization also enables frequency synchronization among RUs, which is the fundamental prerequisite to realize comprehensive time synchronization. Upon providing the RUs with precise timing information using methods such as frequency counting and route latency measurement or protocols similar to PTP, we envisage achieving sub-nanosecond time synchronization among the RUs, empowering the realization of a variety of advanced precise positioning and sensing applications [14].
Figure 1.Concept of clock-synchronized, parallel WDM channel fronthaul structure enabling multifunctional RAN, empowering various applications required in the IMT 2030 usage scenarios [17].
2. PRINCIPLE OF EO COMB CLONING AND CLOCK SYNCHRONIZATION
In this section, we describe the realization of electro-optic (EO) comb cloning and clock synchronization, as shown in Fig. 2. In the suggested framework, an EO comb is employed, with certain comb lines functioning as signal carriers, while a subset of comb lines serves as pilot comb lines and remains unmodulated. These pilot lines carry information about the transmitter’s comb state and Tx’s clock, which are essential for the cloning process and clock distribution.
Figure 2.The principle of EO comb cloning and clock synchronization.
The key enabler for this architecture lies in the inherent characteristics of the EO comb. The EO comb is generated by injecting a seed laser into RF signal-driven electro-optic modulators [20]. The frequencies of the comb lines are given by , where is the center frequency determined by the seed laser, and is the repetition frequency, which matches the RF signal’s frequency. This means that by transmitting the pilot comb lines that contain both and , an identical EO comb can be cloned at the Rx using the same setup [21].
In addition, clock information can be embedded in the comb’s repetition frequency through frequency multiplication. This can be achieved when the clock signal and the RF signal share the same source, their frequency following the multiplication rule , and their phase noise power spectral density (PSD) following (in dB). As a result, when the RF signal drives the electro-optic modulators to produce the EO comb, the clock information is inherently loaded onto the repetition frequency of the comb.
By transmitting the pilot comb lines carrying both the transmitter’s comb state information and the clock information (i.e., and ) alongside the data channel, both the EO comb state and the multiplied clock information can be delivered to the receiver. The receiver can then clone the identical comb employing the same setup as in Tx and use it as a local oscillator. Moreover, the synchronized clock can be extracted through the reverse process—frequency dividing the repetition frequency with its phase noise PSD being (in dB). This brings the additional benefit that the phase noise induced by link transmission is also reduced by through frequency division. In this way, compared to directly loading the clock signal onto the carrier [22], this approach significantly improves its resilience against environmental changes, e.g., mechanical vibration, that degrade phase noise and timing jitter performance [23].
As a result, this approach enables a self-homodyne structure, rendering both frequency offset estimation and carrier phase estimation unnecessary. It also eliminates the need for digital timing recovery in the DSP flow, which accounts for a considerable amount of power consumption in DSP receivers [24]. Additionally, since each RU at the receiver follows the same structure, frequency synchronization is achieved across all RUs, laying the foundation for time synchronization among them.
3. EXPERIMENTAL SETUP
The experimental setup is depicted in Fig. 3. A 1 kHz linewidth laser (NKT Photonics Koheras X15) centered at acts as the seed laser, which is then injected into cascaded low- intensity and phase modulators (IM and PM) driven by a low-noise RF source (Anritsu MG3695A) with a frequency of to produce the EO comb. The driving power of the IM and PM is 22 dBm and 28 dBm, respectively. Its optical spectra are shown in Fig. 4(a). The generated comb lines are initially amplified using a polarization maintaining erbium-doped fiber amplifier (PM-EDFA), then filtered and flattened, with only 15 lines retained, which have the same level of optical-carrier-to-noise ratio (OCNR). These lines are labeled as Ch. #–7 to Ch. #7 from low to high frequency, with the seed laser designated as Ch. #0. The 15 comb lines are segregated into two segments. The three central comb lines (Ch. #0 to #2) remain unmodulated after amplification, preserving information about the center frequency from Ch. #0 and the repetition frequency from the beating of Ch. #1 and Ch. #2. The choice of using three comb lines is to ensure optimal OCNR performance [18]. The remaining comb lines (Ch. #–7 to #–1, #3 to #7), serving as signal carriers, are first amplified, fed into a lithium niobate IQ modulator (Shenzhen HLT Optical Technology), and then polarization multiplexed using a polarization division multiplexing emulator (PDME, insertion loss: 6 dB). Note that we encode the double polarization (DP)-20 GBaud 64-QAM signal onto the carrier using an arbitrary waveform generator (Keysight MG8195A). The signals are generated offline, following the procedure of QAM-mapping, 1:3 upsampling to 60 GSa/s, and finally root raised cosine filtering with . Out-of-band noise is further filtered using a wavelength selective switch (WSS, insertion loss: 6 dB). The clock for the arbitrary waveform generator (Tx) is supplied directly by the 10 MHz clock module of the RF source, ensuring that the clock at Tx and the RF signal driven comb come from the same source. Finally, the modulated signal and the three pilot comb lines are combined using an 80:20 coupler and transmitted through 10 km of single-mode fiber (SMF) with a launch power of 4 dBm to avoid fiber nonlinearity.
Figure 3.Experimental setup for the clock-synchronized, self-homodyne fronthaul structure enabled by EO comb cloning. IM: intensity modulator, PM: phase modulator, RF: RF source, AWG: arbitrary waveform generator, IQ Mod.: in-phase and quadrature modulator, PDME: polarization division multiplexing emulator, WSS: wavelength selective switch, VOA: variable optical attenuator, PD: photodetector, OBPF: optical bandpass filter, Coh. Rx.: coherent receiver, VCO: voltage-controlled oscillator, 1/2: 1/2 frequency divider, 1/125: 1/125 frequency divider, PM-EDFA: polarization maintaining erbium-doped fiber amplifier, EDFA: erbium-doped fiber amplifier, LNA: low-noise amplifier.
Figure 4.Optical spectra of (a) generated carrier comb at Tx (blue line) and cloned comb at Rx (red line) and (b) received signal after 10 km transmission.
At the RUs, the signals are first amplified and then segregated into three parts using a waveshaper. Two of these parts are utilized for clock retrieval and EO comb cloning, while the third filters out the data channel. As shown in the upper branch of the Rx in Fig. 3, two of the three pilot signals, Ch. #1 and Ch. #2, beat at a photodetector and are then amplified by two low-noise electrical amplifiers (LNAs) to obtain the 25 GHz . The beat signal, acting as a reference for the VCO, is input into a servo loop to regulate the VCO’s output frequency. This process ensures that the RF signal generated by the VCO remains in phase with the beat signal, thus exhibiting the same phase characteristics as . The VCO, with an output power of 12 dBm, serves both the clock module and the EO comb cloning module. Its RF spectrum is shown in Fig. 5(a).
Figure 5.(a) RF spectrum of 25 GHz signal generated by VCO. The inset is the 100 MHz clock signal via subsequent frequency dividing. (b) Single-sideband phase noise PSD of 25 GHz RF source (purple curve), 25 GHz VCO RF output with and without servo loop locking (red and yellow curves), and 100 MHz clock signal after frequency dividing (blue curve).
In the clock module, the RF signal generated by VCO, is first frequency divided by 250 times, using a cascaded 1/2 and 1/125 frequency divider, and then filtered by a 100 MHz bandpass filter, resulting in the recovery of a high-quality 100 MHz clock signal, whose RF spectrum is shown in the inset of Fig. 5(a). This clock signal is frequency-synchronized with the Tx side’s clock as it is derived from the recovered . This synchronization not only achieves clock alignment between the CUs/DUs (Tx) and the RUs (Rx) and eliminates the need for digital timing recovery in the DSP, but also ensures that the clock frequencies of all RUs are synchronized.
The other output of the VCO is employed for comb regeneration, facilitated by another segment of the filtering process as follows. In the middle branch, Ch. #0, which has the frequency of , is amplified and filtered using a narrow-band optical bandpass filter (OBPF) with an output power of 15 dBm, and then fed into intensity and phase modulators, all driven by the VCO. This setup mirrors that of the carriers at the Tx end, generating an identical comb that serves as a local oscillator, enabling self-homodyne detection. The input powers of the data signal and LO for the coherent receiver are approximately and 3.5 dBm, respectively. The DSP is conducted offline, which follows the procedure of optical front end correction, matched filtering, resampling, and adaptive equalization (constant modulus algorithm for pre-convergence, then switched to decision-directed mode). The details will be elaborated in Section 5. Note that the channel spacing is specifically set to 25 GHz so that the waveshapers used in the experiment can be replaced by low-cost, off-the-shelf WSSs or integrated arrayed waveguide gratings [25]. Furthermore, by employing integrated low- modulators, as elaborated in Ref. [26], it becomes possible to achieve lower power consumption and cost.
4. RESULTS
A. Low-Timing-Jitter Clock Distribution Delivered by Pilot Comb Lines
Since frequency synchronization is achieved through the delivery and beating of pilot comb lines and then frequency dividing of the recovered , we first compare their performance of the retrieved clock signal and the original RF signal at the Tx in terms of phase noise. Figure 5(b) shows the single-sideband phase noise PSD of the 25 GHz signal generated by the RF source, VCO with and without servo loop locking, and the 100 MHz clock signal post frequency division. The similarity between the phase noise curves of the 25 GHz RF source signal at Tx and the locked VCO signal at Rx validates the successful recovery of through the delivery of pilot comb lines and use of the phase-locked loop. The elevated phase noise for higher offset frequencies ( to ) is attributed to the servo loop. This also indicates that the phase noise and timing jitter performance are mainly restricted by that of the RF source, and can be elevated by using one with better phase noise performance. On the other hand, the significant increase in phase noise of the 25 GHz signal generated by the unlocked VCO, which is the yellow curve, indicates the importance and indispensability of the servo loop. Additionally, the phase noise PSD of the 25 GHz signal generated by the locked VCO and the 100 MHz clock adheres to the frequency dividing principle (in dB), except for the noise in the high-offset-frequency range, which is a result of the noise floor induced by the frequency divider ().
These results affirm the effective conveyance of the clock signal, achieving a total timing jitter of 1.0 ps integrated from 1 Hz to 40 MHz. This means our performance surpasses that of the White Rabbit Protocol in terms of the frequency synchronization, which has a timing jitter of approximately 2 ps integrated from 10 Hz to 40 MHz, as outlined in Table 1. Given that the White Rabbit Protocol relies on Sync-E and a phase-locked loop for clock frequency synchronization and incorporates the PTP for precise time stamp acquisition, we have reason to believe that with accurate timing provided for each RU using time synchronization methods similar to PTP, a clock synchronization performance that exceeds the White Rabbit Protocol can be achieved.
Capacity and Timing Jitter/Phase Noise Comparison with Current Works
Approach
Capacity
Timing Jitter/Phase Noise
Re-scaled Timing Jitter/Phase Noise in This Work
Frequency Range
White Rabbit [14,15]
1.25 Gb/s
2 ps
138 fs
10 Hz–40 MHz
Frequency comb dissemination [27]
1.2 Gb/s
73 fs
104 fs
1 kHz–10 MHz
Phase caching [16]
25.6 Gb/s
−90 dBc/Hz
−87 dBc/Hz
10 Hz
−95 dBc/Hz
−104 dBc/Hz
100 Hz
−95 dBc/Hz
−117 dBc/Hz
1 kHz
−113 dBc/Hz
−113 dBc/Hz
10 kHz
−120 dBc/Hz
−129 dBc/Hz
100 kHz
−131 dBc/Hz
−141 dBc/Hz
1 MHz
−140 dBc/Hz
−152 dBc/Hz
10 MHz
EO comb cloning (our approach)
We also assess the influence of transmission distance on the phase noise characteristics of the clock signal. Note that the received optical power for the photodetector is maintained at 2 dBm using the variable optical attenuator (VOA). As depicted in Fig. 6(a), across scenarios of back-to-back, 4, 10, and 20 km transmission distances, all clock signals exhibit consistent phase noise performance, with their timing jitter only being less than 1.2 ps (integrated from 1 Hz to 40 MHz). This suggests that the link-induced phase noise is minuscule and the transmission distance has minimal impact on the phase noise and timing jitter performance of the pilot signals and clock signal for distances less than 20 km, which is most cases for the fronthaul transmission [28]. This validates the broad applicability of the system for various fronthaul scenarios, irrespective of their distance.
Figure 6.(a) Single-sideband PSD of the 100 MHz post-frequency-dividing VCO signal with phase-locked loop with different transmission distances of back-to-back, 4 km, 10 km, and 20 km, marked in red, yellow, blue, and purple, respectively; (b) timing jitter of the 100 MHz clock with different received optical powers of the photodetector.
We also analyze the power budget of the distributed clock by varying the input power of the photodetector. As illustrated in Fig. 6(b), the timing jitter, integrated from 1 Hz to 40 MHz, remains below 1.5 ps when the optical power ranges between 2 dBm and . However, with optical power levels of and below, the timing jitter increases to over 500 ps due to the failure of servo loop locking. This results in a 15 dB power budget available for further clock dissemination.
B. Clock-Synchronized Self-Homodyne Transmission
Leveraging the synchronized clock between Tx and Rx, we showcase high-capacity fronthaul transmission utilizing a 20 GBaud DP-64-QAM signal. First we validate the necessity and efficacy of clock synchronization. Note that even though here we utilize a self-homodyne structure that ensures the local oscillator is in-phase with the carrier, residual phase noise still exists, which is mainly due to the phase noise induced by optical path mismatch, and phase-locked loops. The phase noise of the former, , is the same for all channels, while the latter, , accumulates times for the th channel, as the electrical field of the LO comb lines can be expressed as [ is the random phase noise], i.e., the outer channel suffers most from residual phase noise (), while the inner the least () [18]. Although the overall residual phase noise is a small value, to fully exclude its potential impact for the demonstration of a synchronized clock, here we select Ch. #–1 as it exhibits the least residual phase noise for characterization.
As depicted in Fig. 7(a), in the absence of any form of clock synchronization, the constellation of the 64-QAM signal appears chaotic and unrecoverable, resulting in a BER of . Introducing a digital timing recovery algorithm in the DSP pipeline renders the constellation clear and recoverable, achieving a BER of , even in the absence of carrier phase estimation and frequency offset estimation, thanks to the self-homodyne structure [Fig. 7(b)]. As for our approach shown in Fig. 7(c), we achieve a DSP-compatible BER of , validating the effectiveness of our methodology. Note that we use 600,000 bits for BER calculation of each channel.
Figure 7.The constellations of the 64-QAM signal for Ch. #–1 under three scenarios: without clock synchronization, with digital timing recovery, and with our proposed approach, and Ch. #6. The DSP omission for each recovered signal’s constellation is indicated at the top, highlighting the DSP omission ratio for each case. Note that the carrier phase estimation omission ratio is elaborated in Appendix A.
Furthermore, we confirm the successful omission of carrier phase estimation and frequency offset estimation in the DSP processes. Even in the case of the channel with the poorest performance due to channel crosstalk and most residual phase noise, Ch. #6, its constellation remains clear, with a BER of , as shown in Fig. 7(d). This underscores the efficacy of the self-homodyne structure, which eliminates the necessity for phase noise tracking in DSP.
Additionally, we assess performance by varying the received optical power (ROP) of the signal across three scenarios: back-to-back electrical synchronization, digital timing recovery enabled synchronization, and our methodology, to compare our performance against the most ideal scenario. Illustrated in Fig. 8(a), when the ROP exceeds , the BER meets the threshold of for the HD-FEC with 14% overhead [29]. A marginal penalty (less than 1 dB and 0.5 dB) is observed between the electrical back-to-back synchronization and digital timing recovery, and our methodology, which is deemed highly satisfactory. And at the Rx end, each channel’s signal has an optical power of approximately after the waveshaper, indicating a power budget of 15 dB available for the received signal.
Figure 8.(a) BER performance of Ch. #–7 to , 3 to 7. All 12 channels used for transmission meet the threshold of for the hard decision FEC with 14% overhead, averaging at . (b) BER versus received optical power of the signal for Ch. #–1. Minor penalty is observed compared to the ideal electrical back to back and most commonly used DSP-synchronized scenario across different received signal optical powers, showcasing the effectiveness of our approach.
We finally showcase the 12-channel WDM transmission using the 20 GBaud DP-64-QAM signal. Across all 12 channels, their BERs all meet the 14% overhead HD-FEC threshold, averaging at , as shown in Fig. 8(b). Note that the inner channel, e.g., Ch. #–1, has the best performance due to the fact that it suffers the least from the phase noise. At the outer channel, the accumulated phase noise and the channel crosstalk both contribute to the worsening of the performance, like Ch. #6 as mentioned earlier. This results in a total capacity of , with the net rate being .
5. DISCUSSION
We first aim to compare the performance of our architecture with the current approaches in terms of capacity and timing jitter/phase noise. We would like to stress that previous work has been focusing mainly on the high-precision-clock distribution, while our work emphasizes achieving simultaneous clock distribution and large capacity transmission within one unified fronthaul architecture. It is important to note that as the timing jitter values are provided in different frequency ranges for various works, we have converted our timing jitter/SSB phase noise values to the corresponding frequency ranges or carrier frequencies of each approach. As shown in Table 1, our approach demonstrates notable achievements in terms of transmission capacity and timing jitter, potentially surpassing the current benchmarks.
Moreover, we evaluate the reduced power dissipation thanks to our clock-synchronized self-homodyne structure. For a typical coherent transmission system, the DSP flows that contribute to DSP consumption at the Rx side usually consist of processes such as chromatic dispersion compensation, digital timing recovery, pulse shaping, and adaptive equalization for residual dispersion including polarization mode dispersion (PMD), frequency offset estimation, carrier phase estimation, and finally error correction. Given that in fronthaul applications, the typical transmission distances are generally no longer than 20 km, the need for chromatic dispersion compensation is greatly reduced and can be excluded from further consideration [30]. Additionally, in the context of fronthaul transmission where the RU forwards the wireless waveform transparently [13,31], i.e., without decoding, the power dissipation associated with FEC decoding is also not considered, as shown in Fig. 9(a).
Figure 9.DSP flows of the traditional coherent transmission and simplified DSP thanks to the clock-synchronized and self-homodyne architecture in our approach.
In this architecture, we achieve the exclusion of the digital timing recovery algorithm through clock synchronization between the CUs/DUs (Tx) and the RUs (Rx), as well as the exclusion of carrier phase estimation and frequency offset estimation thanks to the self-homodyne structure. As estimated in Ref. [32], with the omission of digital timing recovery, carrier phase estimation, and frequency offset estimation in the algorithm, the energy consumption for the DSP process is reduced to 64% of its previous level. By employing a DP-20 GBaud 64-QAM signal for data transmission, a total power saving of 2.6 W for a single WDM channel is achieved due to the simplified DSP approach when implemented in Xilinx Vivado [33]. The detailed estimation is elaborated in Appendix B.
Finally, we would like to discuss the plausibility of complete time synchronization within our architecture and its potential benefits. While currently focusing on frequency synchronization, complete time synchronization can be achieved once all RUs are provided with accurate time, which can be easily obtained using protocols like PTP or frequency counting and route latency measurement. Regarding the advantages, precise time synchronization not only facilitates accurate positioning applications but also enables baud-rate sampling by making the sampling clocks of the Tx and Rx fully synchronized, i.e., the clock phases perfectly aligned. This becomes particularly significant given the high symbol rates involved [34].
Furthermore, when integrated with adaptive polarization control (APC) and bidirectional transmission (BiDi), the need for adaptive equalization in polarization demultiplexing can be further eliminated [35], resulting in a DSP-free architecture that can further significantly reduce power consumption [22,36].
6. CONCLUSION
In conclusion, we have proposed a multifunctional fronthaul architecture that can simultaneously achieve picosecond-level clock distribution and Tb/s, DSP-simplified data transmission. This is achieved by using EO combs as carriers, and delivering adjacent comb line pilots, alongside the WDM data channels. At the Rx side, through the beating of the comb lines, the center frequency and repetition frequency are retrieved, enabling the regeneration of combs as local oscillators for the self-homodyne detection, and therefore omitting the carrier phase estimation and frequency offset estimation in the DSP flows. On top of that, through the frequency dividing of the repetition frequency , a high-quality 100 MHz clock is generated, with its timing jitter only being 1 ps (integrated from 1 Hz to 40 MHz). This clock signal is synchronized with that at the Tx side since it is retrieved from the delivered repetition frequency, which is from the same source as the clock at Tx, realizing the clock synchronization between the CUs/DUs and RUs, further omitting the digital timing recovery in DSP flows. Beyond that, the frequency synchronization between each RU is also realized, laying the solid foundation for comprehensive time synchronization once given the time information using GNSS or PTP, which is anticipated to enable advanced positioning and sensing applications like autonomous car fleets, drones, and VR headsets.
Acknowledgment
Acknowledgment. The authors thank Bibo He, Rongwei Liu, Xu Liu, and Jiachuan Yang for their helpful assistance with the instrument introductions.
APPENDIX A: REALIZATION OF THE OMISSION OF CARRIER PHASE ESTIMATION
In this architecture, we achieve the exclusion of the digital timing recovery algorithm through clock synchronization between the CUs/DUs (Tx) and the RUs (Rx), as well as the exclusion of carrier phase estimation and frequency offset estimation thanks to the self-homodyne structure. This is because, for the cloned comb, its th comb line’s electrical field can be expressed as where is amplitude of the electrical field, is the original phase, and is the link-induced phase noise. This is the same as the carrier , except for the term . This residual phase difference, which arises from the phase noise induced by optical path mismatch, phase-locked loops, and the voltage-controlled oscillator (VCO), is a slowly varying value that remains stable within microseconds. Therefore, we can use the initial symbols as a training sequence to calculate the near-consistent phase difference between the signal and the local oscillator and its value can be used to compensate for all symbols. Here we use the first 4096 symbols out of all 400,000 symbols using a blind phase search to determine their average phase rotation, which is then used to compensate across all data symbols, enabling a carrier-phase-estimation-free decision-directed least mean squares adaptive equalizer to function effectively.
APPENDIX B: ESTIMATION ON THE REDUCED POWER CONSUMPTION WITH SIMPLIFIED DSP
In Ref. [33], it lists the hardware requirements of the implementation in Xilinx Vivado for a Gardner synchronization in the time domain with an oversampling of 4/3, a clock frequency of 250 MHz, 96 symbols per clock cycle (), and 6-bit resolution, as shown in Table 2.
Number of Lookup Tables, Flip-Flops, and DSP Slices Implemented for Gardner Algorithm in Xilinx Vivado [33]
Algorithm
Estimation in Gardner
Correction in Gardner
Lookup tables
1435
35,652
Flip-flops
1932
78,280
DSP slices
97
2016
If we consider using a Xilinx Virtex 7 xc7vx690t board, then using the Xilinx Power Estimator powered by AMD [37], we calculate its core dynamic power to be 2.15 W. Since our system has a 20 GBaud symbol rate, our dynamic power consumption would be .
And according to the simulation in Ref. [32], for a 20 nm CMOS process technology, the energy per information bit consumed by the pulse shaping, timing recovery, PMD compensation, and carrier recovery is 7, 26, 61, 12 pJ/bit, respectively, which attributes to 6%, 25%, 58%, and 11% of the total power consumption, respectively. With the advance of the CMOS technology process, the power consumption for each DSP is reduced, yet it does not change their relative proportion compared to the total consumption. Therefore, a total of is saved for a single WDM channel thanks to our clock-synchronized, self-homodyne structure, which omitted the timing clock recovery, carrier phase estimation, and frequency estimation in the DSP flows.
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