Integrated optoelectronic chips working in the visible spectrum range have promising applications in the fields of augmented reality and virtual reality^[1–3], quantum information processing^[4,5], biosensors^[6], etc^[7,8]. An optical phased array (OPA) can shape and steer light without moving parts and has the advantages of small size and flexible control, which enables these applications on a compact chip^[1,9–11]. Established OPA studies primarily focus on near-infrared and silicon platforms^[12–14] and are hindered by silicon’s transparent window ($>1.2\mathrm{\mu m}$) beyond the visible light range. Silicon nitride is the leading platform of visible light OPA due to its low loss, wide transparent window, high threshold power, and CMOS compatibility^[15–17].

Recently, there have been some studies related to silicon nitride OPA, but due to the reduction in wavelength, the diffraction limit, component size, and component spacing have also decreased, making the requirement for manufacturing accuracy higher and the micro-nanoprocessing more difficult^[9–11,18]. In addition, the thermo-optic (TO) coefficient of silicon nitride is smaller, which makes it more difficult to use TO modulation to control OPA for beam calibration and scanning^[19]. Despite reports on blue OPA and adjustable visible light OPA, the design, processing, and control of visible light OPA still faces challenges^[10,11,20]. An electronic system is needed to control and output the voltage for modulation to control the OPA outgoing beam. A control system including a field programmable gate array (FPGA) and a digital-to-analog converter (DAC) is a feasible method to realize OPA high-speed beam scanning and has been used for infrared OPA^[21,22]. However, the reported output voltage range of existing control systems is too low to meet the needs of silicon nitride OPA, and the versatility of the control systems is poor.

Here, we report a control system that includes an FPGA and a DAC module according to the needs and characteristics of the silicon nitride OPA and the design, calibration, and demonstration of a 532 nm OPA on the silicon nitride platform. As shown in Fig. 1, the OPA chip comprises an edge coupler, a multistage multimode interferometer (MMI) beam splitter tree, a TO phase shifter (PS) array, a set of metal pads connected to the PS, and an emitting grating antenna array. The FPGA-based control system controls the DAC output analog voltages to the PS for modulation. Using a user datagram protocol (UDP) for data transmission and a particle swarm optimization (PSO) algorithm, the system realizes single-shot multivoltage optimization of tens of milliseconds for OPA beam calibration, which greatly shortens the time of OPA beam calibration. The single-shot voltage optimization time is 1 to 3 orders of magnitude shorter than that reported in Refs. [22–24], respectively. The far-field image is captured by a camera and processed by a personal computer (PC) as an upper computer for beam optimization. Using FPGA’s random access memory (RAM) to form a lookup table (LUT), a high-speed voltage configuration of 7.4 µs is realized, which is slightly shorter than that reported in Refs. [14,21]. Using the setup control system, we successfully demonstrated the beam angle calibration and steering in the range of $\pm 24°$ of 532 nm silicon nitride OPA. The test results show that the sidelobe suppression ratio (SLSR) is up to 6.47 dB, and the average full width at half-maximum (FWHM) is 0.4°.

We fabricate a 32-channel OPA based on an inductively coupled plasma-chemical vapor deposition (ICP-CVD) silicon nitride (SiNx) platform with a waveguide loss of $\sim 3.06\mathrm{dB}/\mathrm{cm}$ at 532 nm^[25]. As shown in Fig. 2(a), the OPA chip is glued and fixed on a copper-based printed circuit board (PCB) for fixation and heat dissipation during testing, and bonded through the gold wires, as shown in Fig. 2(b). The structure of the chip is shown in Fig. 2(c), which consists of an edge coupler, a $1\times 32$ beam splitter tree, a 32-channel TO PS, a 32-channel waveguide array, and a 32-channel grating antenna.

As shown in Fig. 2(d), a 532 nm laser is coupled into the waveguide from the edge of the chip and divided into 32 beams of equal power light by the beam splitter tree, whose unit structure is a $1\times 2$ MMI beam splitter, as shown in Fig. 2(e). In the PS, whose structure is shown in Fig. 2(f), the nickel chromium (NiCr) microheaters are 800 µm long, 2000 nm wide, and 200 nm thick NiCr with 3.3 kΩ resistance. The external electrical signal is transmitted to the microheaters through the gold wire, so that the waveguide is heated. Due to the TO effect, the refractive index of the waveguide changes, changing the beam’s phase and resulting in different phase differences between the beams of different channels. The phase change of each channel is positively correlated with the temperature change generated by the electric power of the heater^[26,27]. In addition, because the TO coefficient of silicon nitride ($2.45\times {10}^{-5}{\mathrm{K}}^{-1}$)^[19] is smaller than that of silicon ($1.8\times {10}^{-4}{\mathrm{K}}^{-1}$)^[28], the silicon nitride waveguide needs a larger temperature change to achieve the same phase change as the silicon waveguide under the same conditions. After testing, the heater power per $\pi$-phase-shift ($P_{\pi }$) of our PS is 34 mW, and the relaxation time from the voltage applied to PS to the phase stability of the OPA outgoing beam is about 30 µs. Finally, the beams are emitted by the nonuniform grating antenna with a mean pitch of 1.6 μm; its structure is shown in Fig. 2(g). They form a certain pattern in the far field after interference.

A high-speed phase control circuit is essential for controlling the voltage of the multichannel PS to facilitate OPA beam scanning. Moreover, due to the limitations of the chip manufacturing process, there are random initial phase differences and a thermal cross-talk effect between waveguides, resulting in unknown deviations between the theoretical and practical configuration voltages, which requires a specific system to optimize the corresponding configuration voltage in advance to calibrate each deflection angle of the outgoing beam. Therefore, we built a control system including FPGA and DACs, as shown in Fig. 3(a), which can optimize the voltage and calibrate the deflection angle, then obtain and store a set of practical configuration voltages corresponding to each scanning angle, and quickly configure the voltage to realize beam scanning.

Due to its convenient use, fast processing speed, and high cost-effectiveness, FPGA is used as the center of the control system. Programmed in Verilog, it can be divided into Ethernet-related modules, a RAM module, a data control module, and auxiliary modules. The phase-locked loop (PLL) clock module divides the system clock (50 MHz) into a 200 MHz clock, which is used for Ethernet delay control. The PHY chip (the physical layer chip of Ethernet) receives the data from the PC and transmits it to the FPGA via the reduced gigabit medium independent interface (RGMII), minimizing pin usage. The GMII to RGMII module realizes the conversion of two interface data signals. The address resolution protocol (ARP) module queries the media access control (MAC) address of the target device based on the internet protocol (IP) address. The UDP module analyzes the received data according to the Ethernet protocol to obtain the voltage data. The first-input–first-output (FIFO) module caches and transmits data to prevent data loss due to short-term data bursts. The Ethernet control module manages ARP and UDP, and the data control module controls data output and storage. According to the requirements, the voltage data can be directly transmitted to the DAC module controlled by the PC, which is convenient for the optimization and calibration of the deflection angle, or the data can be stored in the FPGA’s RAM to form a LUT for high-speed voltage configuration.

DAC is suitable and feasible as the driver of the multichannel PS of OPA. The universal voltage output DAC chip is convenient and cheap for use in large-scale DAC conversion. As shown in Fig. 3(b), our 64-channel DAC module, with a size of 35.1 mm × 58.4 mm and 4 universal chips, receives serial data from the FPGA via the serial peripheral interface (SPI) and converts it to an analog voltage without extra voltage followers. So, it requires fewer components, is more reliable, and has a smaller size. The TO coefficient of the silicon nitride waveguide leads to the need for a larger voltage for phase shifting. The DAC module can output a 14-bit voltage with an adjustable range (the maximum output range is 40 V) and a maximum current of $\pm 25\mathrm{mA}$, and has monotonicity and high linearity, meeting the needs of most photoelectric chips for phase shifting. According to the needs of the 532 nm OPA used, the DAC output range is set to 0–20 V (only 0–15 V is actually required). The voltage resolution of the DAC module is $\sim 1.2\mathrm{mV}$, and the corresponding phase shift accuracy is $\sim 5\times {10}^{-4}\mathrm{rad}$. The output voltage range, voltage resolution, conversion speed, and circuit size restrict each other, which leads to the limitation of DAC bandwidth while ensuring that the DAC can achieve the required modulation effect.

In order to calibrate the deflection angle, high-speed communication between the PC and FPGA is essential for transmitting a lot of data to find optimal configuration voltages. Ethernet is the most common communication protocol standard used by current local area networks, known for its low cost, high speed, and strong anti-interference property, especially UDP, which is more efficient than a universal asynchronous receiver transmitter (UART, generally $<1\mathrm{Mbps}$). In the control system, in addition to writing code in the FPGA to implement the analysis of the UDP data, it is necessary for the program to quickly call the network driver of the PC to cooperate, so as to better play the advantages of high-speed communication of UDP. MATLAB, as the upper computer, excels in data processing and Ethernet communication, offering methods like built-in functions, a Java interface, dynamic link library (DLL) calls, and MATLAB-executable (MEX) files for UDP. Table 1 shows the transmission rate tests for UART and these four methods of UDP, as well as the minimum (Min), typical (Typ), and maximum (Max) bit rates under different packet lengths and transmission rate fluctuations. It is worth noting that the transmission rate of the UART method is relatively stable with little fluctuation, while the UDP communication test results are affected by the performance and the network environment of the PC. The practical bit rate is the average of five million transmissions. It can be seen that the transmission rate of calling C++ functions through MEX files is the highest, with an average of $9\times {10}^4$ data packets sent per second. This is because C++ is more efficient and MEX-file is more convenient for MATLAB calls. Despite inevitable rate fluctuations, this method will be used for data transmission between the PC and the FPGA, having no impact on angle calibration and data writing.

It is difficult to avoid the fact that the waveguide carries a random initial phase due to process limitations, which makes the angle of the OPA outgoing beam unable to fully conform to the theoretical results. Therefore, it is necessary to set up a measurement system including the control system, as shown in Fig. 4, to optimize and calibrate the angle. The measurement system is composed of the OPA chip, the control system, and the necessary optical devices. The OPA chip is glued and fixed on a copper-based PCB that is bonded to the OPA through gold wires, which is good for heat dissipation. The 532 nm laser is coupled into the waveguide from the edge of the chip through a fiber. The outgoing beam is collected by an infinity-corrected micro-objective and passes through two lenses ($f_{\text{Lens}1}=180\mathrm{mm}$, $f_{\text{Lens}2}=30\mathrm{mm}$) forming a 4f optical system. After the Fourier transform, due to the interference of light, a certain pattern image is formed in the far field. The aperture placed between the two lenses is used to filter out the light other than the OPA outgoing light and to reduce the influence of ambient light on the measurement results. The position of all optical measuring devices is determined by their focal length. The camera (DCC1645C) is used to capture the image and feed it back to the PC. The light intensity per pixel of the image can be obtained by quantization, which is convenient for rapid optimization and iteration in the PC to find the optimal configuration voltage of an angle. The algorithm in PC optimizes the configuration voltage of each angle according to the change in light intensity. In this process, it needs to communicate with the FPGA many times, constantly change the output voltage of the DAC, and carry out the next step of voltage optimization and iteration according to the feedback image. The improvement of various components in the control system and the formation of a closed-loop measurement system have achieved high-speed and stable control of the PS.

OPA needs many times of voltage optimization for angle calibration. The angle calibration algorithm of the outgoing beam has a significant impact on the calibration speed and beam quality. The brute-force (BF) algorithm changes the voltage applied to each PS in the smallest step to traverse all cases. Although the BF algorithm is effective, the calibration process needs many measurements and iterations that take a long time, sometimes even reaching tens of hours. It is easy to fail to achieve the desired results due to external interference or changes, and it is not suitable for practical application. The hill-climbing (HC) algorithm optimizes the voltage of each channel one by one and takes the optimal solution of the current channel as the initial value of the next channel to find the overall optimal solution. However, because of its own limitations, it is easy to fall into a local optimal solution. The PSO algorithm, with the advantages of fast convergence speed and few parameters^[29,30], can optimize 32 channels of voltage at the same time to find the optimal voltage code without traversing all cases, while the BF algorithm and HC algorithm can only optimize the voltage of one channel at a time. As shown in the algorithm in Sec. 1 in the Supplementary Material, the position of the particle is proportional to the electric power, that is, the voltage is proportional to the square root of the particle position. Compared with the BF algorithm ($7.27\times {10}^{134}$ measurements) and HC algorithm ($5.24\times {10}^5$ measurements), which change the minimum step of the channel one by one, the PSO algorithm, after 3000 measurements, has a similar SLSR to the BF algorithm, which has obvious advantages. Some angles have basically converged at 1000 to 2000 times, and 3000 measurements are the number of times to ensure the convergence of the optimization process after multiple experiments from different angles.

The comparison of the single-shot voltage optimization time in beam calibration under different optimization algorithms, data transmission methods, and camera configurations is shown in Table 2. UDP communication effectively reduces data transmission time during voltage optimization. By boosting the pixel clock and reducing the exposure time of the camera while ensuring the image capture effect, image capture and data feedback accelerate. Due to differences in the output light power of OPA at different angles, it may be necessary to adjust the exposure time according to the captured pictures at various angles to obtain a better optimization effect and ensure that the camera is not overexposed. Because of the benefits of the high-speed voltage configuration and information transmission method, coupled with the improvement of the calibration algorithm, the overall operating time of the calibration process is significantly reduced. The experimental test shows that the single-shot multivoltage optimization of the beam calibration is 30 to 50 ms, and the camera time consumption accounts for more than 75%, although the camera configuration has been optimized. The single-shot voltage optimization time is 1 order of magnitude shorter than that reported in Ref. [23] using the stochastic parallel gradient descent (SPGD) algorithm, and 2 and 3 orders of magnitude shorter than that reported in Refs. [22,24] using the HC algorithm, respectively. When all the optimized voltage data are obtained, the data can be directly written into the RAM of the FPGA via UDP and then realize the high-speed scanning angle control.

The measurement system in Fig. 4 is used for high-speed optimization and calibration of beam steering to maximize the main lobe light intensity of the target angle without additional precalibration or phase acquisition. Figure 5 shows the normalized light intensity curves before and after calibration. The intensity is random before calibration, and the sidelobe suppression effect is deplorable, which is worse than the design. This is caused by OPA processing technology limitations, especially the uneven output beam power of each channel. After calibration, the main lobe at the specified angle is enhanced, and the sidelobes are suppressed. The control system optimizes output voltage for sidelobe suppression, achieving the best SLSR, 6.47 dB.

The voltage configuration controlled by the FPGA can achieve a 7.4 µs high-speed configuration, which is shorter than the relaxation time of OPA. As a result, the beam-scanning process of OPA is limited by the speed of thermo-optic modulation, rather than the limitation of the control system. Section 2 in the Supplementary Material shows the measurement of voltage configuration time. Calibration time is limited by capturing pictures and the data transmission of the camera, and can be reduced with a faster camera. Iterations in the calibration algorithm depend on the OPA structure and the number of PSs. The PSO algorithm reduces the iterations, but it still lags behind the point-wise optimization algorithm^[31] and the SPGD algorithm^[23,32].

After angle-by-angle calibration, we get a set of voltage data corresponding to the optimal SLSR at each angle and store them in RAM, which can be used for rapid scanning. We take the scanning results with an interval of 6° to obtain the far-field image, as shown in Fig. 6(a); the corresponding SLSR and FWHM are shown in Fig. 6(b). Due to limitations in the OPA processing technology, we obtained the average SLSR of 4.07 dB, which is comparable to the blue-light OPA reported in Ref. [10]; the average FWHM is 0.4°. These results are comparable with those obtained in the calibration process, indicating that the calibration method is feasible and repeatable. Table 3 shows the performance comparison of visible-light silicon nitride OPA. In our experiment, only a scanning range of 48° ($-24°$ to $+24°$) was measured, which is mainly due to the use of the Fourier transform characteristics of the lens for far-field testing. Because the numerical aperture of the micro-objective used is 0.45, this physical property determines that the theoretical maximum scanning range that can be collected is only $\pm 26.7°$. It can be further improved by testing the devices on a rotating table to obtain a larger angle range of measurement.

We designed and made a 532 nm silicon nitride OPA and a 64-channel phase control system tailored for TO silicon nitride OPAs. Using the PSO algorithm and UDP transmission, we drastically reduced the single-shot multivoltage optimization time of beam calibration to tens of milliseconds. The control system ensures a high, accurate, and stable driving voltage, reaching a speed of 7.4 µs by storing voltage data in the RAM of the FPGA and meeting most OPA modulation needs. Experimental results showed $\pm 24°$ beam steering with an average SLSR of 4.07 dB and FWHM of 0.4° for the 532 nm OPA. Future work will focus on further refining the control system’s performance, exploring new applications, and advancing the design and processing of visible-light OPAs.