In this paper, an FPGA-based high-speed 9/7 discrete wavelet transform design was presented. To make it easy for the hardware implementation, and accelerate the processing speed, the multi-stage pipeline technique is adopted in the realization of the one-dimensional discrete wavelet transform. And modified lifting scheme is used. At the same time, a CSD coding-based and optimized shift-add operations are adopted to implement multiplier. To reduce the occupation of system resources, a line-based architecture is applied to realize 2-D DWT. Only 3 rows of row transform results can start the column transform. This design has been verified by simulation of MATLAB and ModelSim, and can run at 60 MHz clock frequency, meeting the request for real-time processing of high-speed image.