A third-order hybrid structure noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter(ADC) was designed. The hybrid structure consisted of two stage, a cascaded integrator feed-forward (CIFF) stage and a second-order error feedback (EF) stage. This structure was used to control the feedback residue and enhance the order of the noise transfer function, achieving a three-order noise transfer function. And the Vcm-based switching mode was used to optimize the dynamic offset voltage of comparator. The circuit was designed in a 0.35 μm CMOS process. It consumes 1.87 mW power when operating at a 2 MS/s sampling frequency and an oversampling ratio of 8 with a 3.3 V supply. The proposed NS SAR ADC achieves a 87.93 dB SNDR and a 14.3 bit ENOB, enhancing the ENOB by 6.3 bit on the basis of traditional 8-bit SAR ADC.