In high-speed interface circuits, receivers typically use Continuous-Time Linear Equalizer (CTLE) to eliminate the effects of Inter-Symbol Interference (ISI) on signal transmission. In order to improve the high-frequency gain of the CTLE circuit and reduce the chip area, a CTLE circuit with a maximum rate of 50Gbps was designed based on the UMC (United Microelectronics Corporation) 28nm process. Its main circuit was composed of a two-stage CTLE circuit with a trans-admittance transimpedance (TAS-TIS) structure and feed-forward path. On the basis of traditional CTLE, the active inductor was used as the load, the transimpedance amplifier was built based on the inverter, and the feed-forward path was added to the input tube, which effectively expanded the operating frequency of the circuit. The simulation results show that the eye widths of the 40Gbps PAM4 (4-Level Pulse Amplitude Modulation) signal, 50Gbps PAM4 signal and 28Gbps NRZ (Non Return Zero Code) signal reach 0.68, 0.5, 0.92 code element spacing (UI) respectively, which can meet the requirements of the post-stage circuit for input signals. It is of great significance to improve the overall transmission data rate.