Large scale and high integration of IRFPA device is the core of high spatial resolution infrared imaging. With the development of the high integration IRFPA technology, a 640×512 readout integrated circuit(ROIC) of IRFPA with 15 μm pixel pitch was presented. In order to improve SNR and integration time, one technology method of 2 by 2 pixels sharing an integration capacitor was proposed and the DI architecture was chosen as the input stage, thus the maximum effective charge capacity can reach 20 Me-/pixel. And two levels of charge capacity can be chosen for the readout of different photocurrents.Moreover, current bias circuits were designed for the analog signal chain ciruit to lower the noise and improve the bias current accuracy for buffers. According to the simulation results, the circuit achieves 108 Hz frame rate, less than 110 mW and 99.99% linearity. The circuit was taped out by CSMC 0.18 μm 1P4M 3.3 V CMOS process. The preliminary test results under room temperature show that the working current is normal and the bias switches can be adjusted and the circuit can work normally.