The failure behaviors of memory chips under ESD and electromagnetic interference (EMI) have been characterized by many researches, whereas the frequency response characteristics of continuous wave immunity of SRAM has not been researched yet. The failure behavior and mechanism of SRAM under RF EMI (RFI) was studied in this paper. The SRAM chips RFI testing results revealed that SRAM failure behavior was related to its operating state. Transistor-level simulation was carried out by Hspice. Results showed that the SRAM was highly immune to interference within data hold and weakly immune to interference within read/write state. Further study on the failure mechanism revealed that power-side disturbances caused drift and jitter in the path delay, resulting in SRAM read and write failure. This study could provide guidance for the reliability design of memory or system on chip.