Design and verification of data acquisition clock circuit based on dual-loop phase-locked loop

Zhi LIU; Guodong GAO; Junhui YUE; Jianshe CAO; Yaoyao DU; Huizhou MA; Jun HE; Qiang YE; Xuhui TANG; Yukun LI; Jing YANG; Shujun WEI

doi:10.11889/j.0253-3219.2022.hjs.45.100401

[1] ZHAO Jijiu, YIN Zhaosheng[M]. Particle accelerator technology(2006).

[2] SUI Yanfeng, DU Yaoyao, YE Qiang et al. Development of digital beam position monitor electronics system based on BEPCⅡ[J]. Atomic Energy Science and Technology, 54, 172-178(2020).

[3] Gao B, Chen F Z, Zhou Y M et al. Bunch-by-bunch beam lifetime measurement at SSRF[J]. Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, 1015, 165758(2021).

[4] ZHANG Yongwei. A new method for testing high-speed ADC dynamic performance parameters[J]. Shipboard Electronic Countermeasure, 37, 56-59(2014).

[5] REN Shengjun, CHEN Shaochang. Analysis of the influence of ADC performance on radar system[J]. Ship Electronic Engineering, 37, 60-65(2017).

[6] ZHANG Fan. Key technology to improve SFDR performance of broadband high speed ADC[J]. Electronics Quality, 43-49(2019).

[7] LYU Fangxing. Photonic time-interleaved ADC based on optical clock distribution[J]. Electronic Measurement Technology, 44, 17-22(2021).

[8] Brannon Brad. Aperture uncertainty and ADC system performance[EB/OL]. https://www.analog.com/media/cn/technical-documentation/application-notes/an-501_cn.pdf

[9] ZHANG Zhiqiang, RUAN Liting, NI Tao et al. Calculation of effective numbers of bits for the analog-to-digital converter[J]. Electronic Science and Technology, 23, 84-85, 110(2010).

[10] PU Mingzhen, ZHAO Hongliang, XIAN Zhuolin et al. Design of low-spur and low-phase-noise CPPLL[J]. Research & Progress of SSE, 41, 285-290(2021).

[11] ZENG Zhaoquan, GONG Lijiao, LI Hongyue. Modeling and simulation of charge pump phase-locked loop circuit[J]. Automation & Instrumentation, 37, 79-85, 90(2022).

[12] Slightom Kyle. Dual-loop clock generator cleans jitter, provides multiple high-frequency outputs[EB/OL]. https://www.analog.com/en/analog-dialogue/articles/dual-loop-clock-generator.html

[13] Instruments Texas. LMK04610 ultra-low noise and low power JESD204B compliant clock jitter cleaner with dual loop PLLs[EB/OL]. https://www.ti.com/product/LMK04610

[14] Instruments Texas. LMK0461x phase noise performance with DC-DC converters[EB/OL]. https://www.ti.com/lit/an/snaa308b/snaa308b.pdf

[15] WANG Li, WU Jie. Influence of power supply noise on the performance of ADC[J]. Nuclear Techniques, 43, 110402(2020).

[16] REN Qinglian, GAO Wenhua, GUO Ping. Design and simulation of passive loop filter of third-order PLL[J]. Journal of Sichuan Ordnance, 35, 101-104(2014).

[17] Instruments Texas. Clock design tool v1.1 instructions user's guide[EB/OL]. https://www.ti.com/lit/ug/snau082/snau082.pdf

[18] XIAO Chengcheng, YIN Zhe, ZHANG Junqiang et al. Design and test of a C band local oscillator and clock device in LLRF[J]. Nuclear Techniques, 44, 010201(2021).