• NUCLEAR TECHNIQUES
  • Vol. 45, Issue 10, 100401 (2022)
Zhi LIU1, Guodong GAO1、2, Junhui YUE1, Jianshe CAO1、2, Yaoyao DU1, Huizhou MA1, Jun HE1, Qiang YE1, Xuhui TANG1、2, Yukun LI1、2, Jing YANG1、2, and Shujun WEI1、2、*
Author Affiliations
  • 1Institute of High Energy Physics, Chinese Academy of Sciences, Beijing 100049, China
  • 2University of Chinese Academy of Sciences, Beijing 100049, China
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    DOI: 10.11889/j.0253-3219.2022.hjs.45.100401 Cite this Article
    Zhi LIU, Guodong GAO, Junhui YUE, Jianshe CAO, Yaoyao DU, Huizhou MA, Jun HE, Qiang YE, Xuhui TANG, Yukun LI, Jing YANG, Shujun WEI. Design and verification of data acquisition clock circuit based on dual-loop phase-locked loop[J]. NUCLEAR TECHNIQUES, 2022, 45(10): 100401 Copy Citation Text show less

    Abstract

    Background

    Digital measurement system based on ADCs (analog-to-digital converter) has higher requirement on the signal to noise ratio (SNR) of sampled data. Among all the factors, the jitter of sampling clock has the most prominent effect on SNR.

    Purpose

    This study aims to design a clock circuit based on dual-loop phase-locked loop to reduce the jitter of digital measurement system input clock.

    Methods

    First of all, the influence of clock jitter on digital measurement system was analyzed. Then, the LMK04610 chip with dual loop PLL architecture of Texas Instruments was employed to design and implement a dual-loop phase-locked loop jitter cleaner circuit. The cores of this design were power supply design and the loop filter design. At last, the performance of the circuit was tested by using Rodschwarz phase noise analyzer.

    Results

    After testing, the dual-loop phase-locked loop jitter cleaner circuit can reduce the jitter of the 62.475 MHz source clock from more than 7 ps to less than 2 ps with output frequency of 499.8 MHz. The SNR of the sampled data is close to the theoretical value.

    Conclusions

    Dual-loop phase-locked loop jitter cleaner circuit has a good result and can provide reference for designers of digital measurement system.